The known Fibonacci code adders have a low operational speed since they function in a synchronous mode when the control input of the adder receives short control pulses. During each cycle of the addition process, the intermediate sum and carry codewords are formed which are stored in the registers and the intermediate sum codeword is then reduced to the minimal form. The next cycle deals with the summation of the stored codewords of the intermediate sum and carry, and new codewords are then formed, etc. The process is repeated until the carry contains 0's and the sum obtained corresponds to the minimal form. The maximum number of cycles for the described adder is equal to n/2 where n is the length of the augend and addend in the form of a Fibonacci code.
The length of a single addition cycle must be sufficient for the intermediate or final result of addition to be reduced to the minimal form under the most unfavorable conditions determined by an expression (n/2) .tau..sub.1, where .tau..sub.1 is the time required for an elementary convolution involving a group of p+2 bit positions. Thus, the maximum addition time will be T.sub.max =(n.sup.2 /4) .tau..sub.1.
The described addition process requires that parallel half-adders be available for each pair of identical bit position of the augend and addend, each half-adder comprising an adder modulo 2 and an AND gate.
The numbers belonging to Fibonacci number systems make it possible to create such an algorithm of addition for p-numbers in which the augend and addend are first represented in a partially devolved form, which means that a 1 in the ith bit position of the original augend (addend) is replaced by 1's in the i-1)th and (i-p-1)th bit positions according to the known relation describing Fibonacci p-numbers: EQU .phi..sub.p (k)=.phi..sub.p (k-1)+.phi..sub.p (k-p-1) (1)
where .phi..sub.p (k) is the weight of the kth bit position.
After the values of the augend and addend in the partially devolved form are placed into the corresponding registers, the augend is reduced to the minimal form and 1's from the codeword of the addend are transferred into the augend register provided the value of the identical bit position of the augend is 0. Thus, conventional addition is replaced in the case of Fibonacci number systems by an operation in which the augend and addend are reduced concurrently to the minimal form.